A 16-element 140-160-GHz phased array transceiver is reported. The chipset is fabricated using STMicroelectronics' 55-nm SiGe BiCMOS process. Five different chips are implemented: a 4-channel transmitter with a maximum gain per channel of 15 dB and 0-dBm saturated output power; a 4-channel receiver with a maximum gain of 8 dB, a -10.4-dBm input 1-dB compression point (IP1 dB), and a minimum noise figure (NF) of 15.6 dB per channel; a 0-1-GHz to 140-160-GHz I/Q up-converter with integrated frequency doubler, exhibiting a -13.5-dB conversion gain (CG) and -6-dBm output 1-dB compression point using a 70-80-GHz local oscillator (LO); a 140-160-GHz to 0-1-GHz I/Q down-converter with integrated frequency doubler, exhibiting a CG of 0 dB and IP1 dB of 0 dBm using a 70-80-GHz LO and an 11.67-13.33-GHz to 70-80-GHz x6 frequency multiplier for the LO, delivering 5.6-dBm maximum output power. The chips are assembled together with 16 cavity-backed aperture-coupled patch antennas using a high-performance and low-cost commercial PCB, supported over a heat sink. The main challenges encountered during the integration of the proposed system are also discussed. The complete system is used to build a wireless radio link in the laboratory, demonstrating 2-D beam steering in a range of +/- 30 degrees.

This article presents a high-performance frequency-domain chipless RFID reader with vector background subtraction capabilities, implemented in a software-defined radio (SDR) for the first time. The proposed reader is low-cost, compact size, and versatile. It is implemented in a USRP N210 paired to a modified CBX-40 daughterboard, enabling magnitude and phase data acquisition in a monostatic (one antenna) set up. The reader can perform a vector background subtraction operation between two complex measurements (with and without a chipless tag) to suppress the self-interference (SI) that hinders the response of the tag and provide 40 dB of dynamic range. To demonstrate the performance of the reader, the spectral signatures of three frequency-coded (FC) tags with four resonant frequencies are captured over the 1.5-4-GHz band scanned with 10-MHz resolution in 251 ms, obtaining comparable measurements to those of an expensive laboratory vector network analyzer (VNA) from 20 to 40 cm. The detected resonant frequency offset between both devices is Delta f(r) <= 4.18% . It is also demonstrated that the proposed reader can track a resonant frequency shift and therefore be used in real-time sensing applications.

This article presents a wireless temperature sensor tag able to work in both fully passive mode and in semi-passive mode when assisted by a flexible thermoelectric generator (TEG). The sensor tag consists of an EPC C1G2/ISO 18000-6C ultrahigh-frequency (UHF) radio frequency identification (RFID) integrated circuit (IC) connected to a low-power microcontroller unit (MCU) that samples and collects the temperature from a digital temperature sensor. With a temperature gradient as low as 2.5 degrees C, the test results show that the TEG provides an output power of 400 mu W with an output voltage of 40 mV. By means of an up-converter in order to boost the TEG output voltage, this harvester supplies the power required to the sensor tag for a 2-conv/s data rate in semi-passive mode. Moreover, when the tag operates in semi-passive mode, a communication range of 22.2 m is measured for a 2-W effective radiated power (ERP) reader. To the best of our knowledge, the proposed TEG-assisted sensor tag shows the longest communication range and the only one that provides stable external power at low-temperature gradients. The measured performance and the chosen architecture allow using the wireless sensor in multiple industrial or biomedical applications.

This letter presents the design of a 140-160 GHz vector-modulator-type phase shifter, integrated in a 55-nm BiCMOS technology. The circuit is optimized to minimize the occupied area and maximize the linearity, facilitating its integration in D-band phased arrays. Test results show an average insertion loss of 4.5 dB, an OP 1 dB of -3.7 dBm, and rms gain/phase errors lower than 1.4 dB and 7.5 degrees. The circuit core occupies 0.05 mm(2), consuming less than 66 mW of dc power.

In this paper, a novel Radio-Frequency Identification (RFID) tag for "pick to light" applications is presented. The proposed tag architecture shows the implementation of a novel voltage limiter and a supply voltage (VDD) monitoring circuit to guarantee a correct operation between the tag and the reader for the "pick to light" application. The feasibility to power the tag with different photovoltaic cells is also analyzed, showing the influence of the illuminance level (lx), type of source light (fluorescent, LED or halogen) and type of photovoltaic cell (photodiode or solar cell) on the amount of harvested energy. Measurements show that the photodiodes present a power per unit package area for low illuminance levels (500 lx) of around 0.08 mu W/mm(2), which is slightly higher than the measured one for a solar cell of 0.06 mu W/mm(2). However, solar cells present a more compact design for the same absolute harvested power due to the large number of required photodiodes in parallel. Finally, an RFID tag prototype for "pick to light" applications is implemented, showing an operation range of 3.7 m in fully passive mode. This operation range can be significantly increased to 21 m when the tag is powered by a solar cell with an illuminance level as low as 100 lx and a halogen bulb as source light.

Changes in ambient temperature or chip temperature result in variations in the in-phase and quadrature (I/Q) gain and phase imbalance. As a consequence, the overall system performance can be seriously degraded, especially in wideband multi-Gb/s systems, where the I/Q imbalance is highly selective in frequency. Unless appropriately considered, temperature drifts can decrease the image rejection ratio (IRR) of the transmitter. This article presents a novel compensation method for temperature-dependent transmitter I/Q imbalance over the entire temperature range. It consists of a simple predistortion technique that, based on a few factory characterizations of gain and phase imbalance, is able to estimate and correct the I/Q imbalance at any temperature, without interrupting the normal functionality of the system. The proposed method is assessed in a 2-GHz, 64-QAM transceiver implemented with real hardware. The measurements show that the proposed approach is able to keep the IRR greater than 35 dB in the entire bandwidth and an error vector magnitude (EVM) lower than 3 over a temperature range of 70 C.

This letter presents the design of a compact, wideband, and high-efficiency E-band power amplifier, integrated in a 0.13-mu m BiCMOS process and occupying 0.3 mm(2). It consists of a single-stage balanced amplifier, with HBT transistors in cascode configuration. The power amplifier (PA) is biased in class AB, with a dc consumption of 156 mW. A compact bias circuit is employed to achieve temperature robustness, while the layout is optimized for wideband and highly efficient operation. Measurements show a peak power gain of 15.3 dB at 83 GHz, with a 29.3% fractional bandwidth and less than 1-dB degradation over a 25 degrees C-85 degrees C temperature range. The peak output power at saturation and 1-dB compression is 18.6 and 13.6 dBm, respectively, and the maximum power-added efficiency (PAE) is 30.7%.

This paper presents the design of a compact and wide bandwidth millimeter-wave power detector, integrated at the output of an E-band power amplifier and implemented in a 55-nm SiGe BiCMOS process. It is based on a nonlinear PMOS detector core, and its measured output voltage tracks the output power of the PA from 67 to 90GHz. It provides an insertion loss lower than 0.2dB, and its responsivity can be tuned between 8 and 17V/W. The output bandwidth is bigger than 3GHz, which allows built-in self-test when transmitting multigigabit millimeter-wave signals.

This letter presents a 15-21 GHz I/Q upconverter, based on two Gilbert-cell mixers with an on-chip wideband linearization loop that extends the linear region and allows power efficient operation at backoff power levels. A quadrature LO signal is generated using an integrated two-stage polyphase filter. Measurements show a conversion gain of -5.5 dB, an output 1-dB compression point of 0 dBm, and an image suppression of 40 dB over the 6-GHz output bandwidth. An error vector magnitude of 3.5% is obtained for a 10-Gb/s 64-QAM signal with a bandwidth of 2 GHz. The circuit is integrated in a 55-nm BiCMOS process and occupies 1.07 mm2. The dc power consumption is 61 mW.

This paper presents the design of a wideband and high-linearity E-band transmitter integrated in a 55-nm SiGe BiCMOS technology. It consists of a double-balanced bipolar ring mixer which upconverts a 16-21-GHz IF signal to the 71-76- and 81-86-GHz bands by the use of a 55/65-GHz local oscillator signal, followed by a broadband power amplifier which employs 2-way output power combining using an integrated low-loss balun transformer. The transmitter exhibits an average conversion gain of 24 dB and 22 dB at the 71-76- and 81-86-GHz bands, respectively, with an output 1-dB compression point greater than 14 and 11.5 dBm at each band. A maximum output power of 16.8 dBm is measured at 71 GHz. The dc power consumption is 575 mW. The presented transmitter is used to demonstrate the transmission of a 10.12-Gb/s 64 quadrature amplitude modulated signal with a spectral efficiency of 5.06 bit/s/Hz, which makes it suitable for use in future highcapacity backhaul and fronthaul point-to-point links.

This book presents design methods and considerations for digitally-assisted wideband millimeter-wave transmitters. It addresses comprehensively both RF design and digital implementation simultaneously, in order to design energy- and cost-efficient high-performance transmitters for mm-wave high-speed communications. It covers the complete design flow, from link budget assessment to the transistor-level design of different RF front-end blocks, such as mixers and power amplifiers, presenting different alternatives and discussing the existing trade-offs. The authors also analyze the effect of the imperfections of these blocks in the overall performance, while describing techniques to correct and compensate for them digitally. Well-known techniques are revisited, and some new ones are described, giving examples of their applications and proving them in real integrated circuits.