The conventional way of studying corrosion in marine environments is by installing corrosion coupons. Instead, this paper presents an experimental field study using an unattended corrosion sensor developed on the basis of ultrasound (US) technology to assess the thickness loss caused by general atmospheric corrosion on land close to the sea (coastal region). The system described here uses FPGA, low-power microcontroller, analog front-end devices in the sensor node, and a Beaglebone black wireless board for posting data to a server. The overall system is small, operates at low power, and was deployed at Gran Canaria to detect the thickness loss of an S355 steel sample and consequently estimate the corrosion rate. This experiment aims to demonstrate the system's viability in marine environments and its potential to monitor corrosion in offshore wind turbines. In a day, the system takes four sets of measurements in 6 hour intervals, and each set consists of 5 consecutive measurements. Over the course of 5 months, the proposed experiment allowed for us to continuously monitor the corrosion rate in an equivalent corrosion process to an average thickness loss rate of 0.134 mm/year.

The ultrasound technique is a well-known non-destructive and efficient testing method for on-line corrosion monitoring. Wall thickness loss rate is the major parameter that defines the corrosion process in this approach. This paper presents a smart corrosion monitoring system for offshore wind turbines based on the ultrasound pulse-echo technique. The solution is first developed as an ultrasound testbed with the aim of upgrading it into a low-cost and low-power miniaturized system to be deployed inside offshore wind turbines. This paper discusses different important stages of the presented monitoring system as design methodology, the precision of the measurements, and system performance verification. The obtained results during the testing of a variety of samples show meaningful information about the thickness loss due to corrosion. Furthermore, the developed system allows us to measure the Time-of-Flight (ToF) with high precision on steel samples of different thicknesses and on coated steel samples using the offshore standard coating NORSOK 7A.

In this paper, we propose a flexible Fog Computing architecture in which the main features are that it allows us to select among two different communication links (WiFi and LoRa) on the fly and offers a low-power solution, thanks to the applied power management strategies at hardware and firmware level. The proposed Fog Computing architecture is formed by sensor nodes and an Internet of Things (IoT) gateway. In the case of LoRa, we have the choice of implementing the LoRaWAN and Application servers on the cloud or on the IoT gateway, avoiding, in this case, to send data to the Cloud. Additionally, we have presented an specific setup and methodology with the aim of measuring the sensor node's power consumption and making sure there is a fair comparison between the different alternatives among the two selected wireless communication links by varying the duty cycle, the size of the payload, and the Spreading Factor (SF). This research work is in the scope of the STARPORTS Interconnecta Project, where we have deployed two sensor nodes in the offshore platform of PLOCAN, which communicate with the IoT gateway located in the PLOCAN premises. In this case, we have used LoRa communications due to the required large distance between the IoT gateway and the nodes in the offshore platform (in the range of kilometers). This deployment demonstrates that the proposed solution operates in a real environment and that it is a low-power and robust approach since it is sending data to the IoT gateway during more than one year and it continues working.

This paper presents an area-efficient variable-length FFT algorithm for DVB-T2 receivers. A matrix-based approach is used to achieve a novel radix 2(8) algorithm that fulfils the DVB-T2 specifications. Several implementation techniques are proposed to apply in order to reduce the FFT core area, such as a variable datapath scaling approach, a memoryless CORDIC algorithm and an efficient FIFO implementation. The layout of the FFT processor is designed in XFAB 0.18 mu m CMOS technology. The proposed variable-length processor occupies a layout area of 6.75 mm(2). Compared with the DVB-T2 designs in the literature, the proposed FFT processor presents the most area-efficient implementation. Furthermore, it provides a good power efficiency in the lower modes.

Comparison at implementation level of several pipeline-SDF radix 2(k) FFT architectures is proposed in order to obtain efficient algorithms for DVB-T2 receivers. In the analysis, the area and performance of the algorithms are compared. A variable datapath optimisation has been added to the comparison.