Nuestros investigadores

Roque José Berenguer Pérez

Publicaciones científicas más recientes (desde 2010)

Autores: del Río, David, (Autor de correspondencia); Gurutzeaga, Iñaki; Beriain, Andoni; et al.
ISSN 1531-1309  Vol. 29  Nº 5  2019  págs. 351 - 353
This letter presents the design of a compact, wideband, and high-efficiency E-band power amplifier, integrated in a 0.13-mu m BiCMOS process and occupying 0.3 mm(2). It consists of a single-stage balanced amplifier, with HBT transistors in cascode configuration. The power amplifier (PA) is biased in class AB, with a dc consumption of 156 mW. A compact bias circuit is employed to achieve temperature robustness, while the layout is optimized for wideband and highly efficient operation. Measurements show a peak power gain of 15.3 dB at 83 GHz, with a 29.3% fractional bandwidth and less than 1-dB degradation over a 25 degrees C-85 degrees C temperature range. The peak output power at saturation and 1-dB compression is 18.6 and 13.6 dBm, respectively, and the maximum power-added efficiency (PAE) is 30.7%.
Autores: del Río, David, (Autor de correspondencia); Gurutzeaga, Iñaki; Rezola, Ainhoa; et al.
ISSN 0098-9886  Vol. 46  Nº 3  2018  págs. 366 - 374
This paper presents the design of a compact and wide bandwidth millimeter-wave power detector, integrated at the output of an E-band power amplifier and implemented in a 55-nm SiGe BiCMOS process. It is based on a nonlinear PMOS detector core, and its measured output voltage tracks the output power of the PA from 67 to 90GHz. It provides an insertion loss lower than 0.2dB, and its responsivity can be tuned between 8 and 17V/W. The output bandwidth is bigger than 3GHz, which allows built-in self-test when transmitting multigigabit millimeter-wave signals.
Autores: Liao, D.; Wang, H.; Foster Dai, F.; et al.
ISSN 0018-9200  Vol. 52  Nº 5  2017  págs. 1210 - 1220
Autores: Rezola, Ainhoa; Sevillano, Juan Francisco; Gurutzeaga, Iñaki; et al.
ISSN 0018-9480  Vol. 65  Nº 11  2017  págs. 4758 - 4769
This paper addresses the estimation and compensation of I/Q imbalance, one of the most prominent impairments found in wideband zero-intermediate frequency transceivers (TRxs). The I/Q imbalance encountered in this kind of TRx comprises not only frequency-selective gain and phase imbalance but also delay imbalance. Unless appropriate compensation is applied, the I/Q imbalance significantly degrades the performance of a communication system. This paper presents a novel compensation technique for transmitter I/Q imbalance based on built-in-self-calibration, a low cost and robust compensation technique that enables manufacturing as well as in-field calibration with low computational complexity. The method's performance is evaluated in a TRx with 64-quadratic-amplitude modulation and 2 GHz of bandwidth implemented with real hardware. The measurements show that the proposed technique achieves an image rejection ratio greater than 35 dB in the entire 2 GHz bandwidth and an error vector magnitude lower than 3%.
Autores: del Río, David; Gurutzeaga, Iñaki; Rezola, Ainhoa; et al.
ISSN 1531-1309  Vol. 27  Nº 5  2017  págs. 512 - 514
This letter presents a 15-21 GHz I/Q upconverter, based on two Gilbert-cell mixers with an on-chip wideband linearization loop that extends the linear region and allows power efficient operation at backoff power levels. A quadrature LO signal is generated using an integrated two-stage polyphase filter. Measurements show a conversion gain of -5.5 dB, an output 1-dB compression point of 0 dBm, and an image suppression of 40 dB over the 6-GHz output bandwidth. An error vector magnitude of 3.5% is obtained for a 10-Gb/s 64-QAM signal with a bandwidth of 2 GHz. The circuit is integrated in a 55-nm BiCMOS process and occupies 1.07 mm2. The dc power consumption is 61 mW.
Autores: del Río, David; Gurutzeaga, Iñaki; Rezola, Ainhoa; et al.
ISSN 0018-9480  Vol. 65  Nº 8  2017  págs. 2990 - 3001
This paper presents the design of a wideband and high-linearity E-band transmitter integrated in a 55-nm SiGe BiCMOS technology. It consists of a double-balanced bipolar ring mixer which upconverts a 16-21-GHz IF signal to the 71-76- and 81-86-GHz bands by the use of a 55/65-GHz local oscillator signal, followed by a broadband power amplifier which employs 2-way output power combining using an integrated low-loss balun transformer. The transmitter exhibits an average conversion gain of 24 dB and 22 dB at the 71-76- and 81-86-GHz bands, respectively, with an output 1-dB compression point greater than 14 and 11.5 dBm at each band. A maximum output power of 16.8 dBm is measured at 71 GHz. The dc power consumption is 575 mW. The presented transmitter is used to demonstrate the transmission of a 10.12-Gb/s 64 quadrature amplitude modulated signal with a spectral efficiency of 5.06 bit/s/Hz, which makes it suitable for use in future highcapacity backhaul and fronthaul point-to-point links.
Autores: del Río, David; Gurutzeaga, Iñaki; Rezola, Alberto; et al.
ISSN 1531-1309  Vol. 27  Nº 5  2017  págs. 512 - 514
Autores: Jauregi, I.; Solar, Héctor; Beriain, Andoni; et al.
ISSN 1530-437X  Vol. 17  Nº 5  2017  págs. 1471 - 1478
The number of wireless medical wearables has increased in recent years and is revolutionizing the current healthcare system. However, the state-of-the-art systems still need to be improved, as they are bulky, battery powered, and so require maintenance. On the contrary, battery-free wearables have unlimited lifetimes, are smaller, and are cheaper. This paper describes a design of a battery free wearable system that measures the skin temperature of the human body while at the same time collects energy from body heat. The system is composed of an UHF RFID temperature sensor tag located on the arm of the patient. It is assisted with extra power supply from a power harvesting module that stores the thermal energy dissipated from the neck of the patient. This paper presents the experimental results of the stored thermal energy, and characterizes the module in different conditions, e.g., still, walking indoors, and walking outdoors. Finally, the tag is tested in a fully passive condition and when it is power assisted. Our experimental results show that the communication range of the RFID sensor is improved by 100% when measurements are done every 750 ms and by 75% when measurements are done every 1000 ms when the sensor is assisted with the power harvesting module.
Autores: Beriain, Andoni, (Autor de correspondencia); Sevillano, Juan Francisco; et al.
ISSN 0925-1030  Vol. 91  Nº 3  2017  págs. 433 - 444
This work presents a nonius time to digital converter (TDC) adapted to a passive RF identification (RFID) pressure sensor tag. The proposed converter exploits the characteristics of time-based sensor interfaces and allows reducing voltage supply and power consumption while maintaining resolution and conversion efficiency. The nonius TDC has been designed and fabricated using the TSMC 90 nm standard CMOS technology. The main blocks of the converter are described and both the resolution adjustment and measurement processes are explained in detail. Measurement results show 10.49 bits of effective resolution for an input time range from 28.19 to 42.93 mu s. With a sampling rate of 19 KS/s the converter has a conversion efficiency of 0.395 pJ/bit with a voltage supply of only 0.6 V. This characteristics in the proposed nonius TDC enables an increased reading range of the passive RFID pressure sensor tag.
Autores: del Río, David; Gurutzeaga, Iñaki; Solar, Héctor; et al.
ISSN 0167-9260  Vol. 52  2016  págs. 208 - 216
This paper describes a method to design mmW PAs, by modeling the electromagnetic behavior of all the passive structures and the layout interconnections using a 3D-EM solver. It allows the optimization of the quality factor of capacitors (Q-factors > 20 can be obtained at 80 GHz), the access points and arrangement of the power transistor cells. The method is applied to the design and optimization of an E-Band PA implemented in a 55 nm SiGe BiCMOS technology. The PA presents a maximum power gain of 21.7 dB at 74 GHz, with a 3-dB bandwidth covering from 72.6 to 75.6 GHz. The maximum output P1dB is 13.8 dBm at 75 GHz and the peak PAE is 14.1%. (C) 2015 Elsevier B.V. All rights reserved.
Autores: Beriain, Andoni, (Autor de correspondencia); Gutiérrez, Íñigo; Solar, Héctor; et al.
Revista: SENSORS
ISSN 1424-8220  Vol. 15  Nº 9  2015  págs. 21554 - 21566
This paper presents an ultra low-power and low-voltage pulse-width modulation based ratiometric capacitive sensor interface. The interface was designed and fabricated in a standard 90 nm CMOS 1P9M technology. The measurements show an effective resolution of 10 bits using 0.5 V of supply voltage. The active occupied area is only 0.0045 mm(2) and the Figure of Merit (FOM), which takes into account the energy required per conversion bit, is 0.43 pJ/bit. Furthermore, the results show low sensitivity to PVT variations due to the proposed ratiometric architecture. In addition, the sensor interface was connected to a commercial pressure transducer and the measurements of the resulting complete pressure sensor show a FOM of 0.226 pJ/bit with an effective linear resolution of 7.64 bits. The results validate the use of the proposed interface as part of a pressure sensor, and its low-power and low-voltage characteristics make it suitable for wireless sensor networks and low power consumer electronics.
Autores: Rezola, Ainhoa; Sevillano, Juan Francisco; del Río, David; et al.
ISSN 1998-4480  Vol. 9  2015  págs. 98 - 104
Autores: Rezola, Ainhoa; Sevillano, Juan Francisco; Leyh, M.; et al.
ISSN 1942-2601  Vol. 8  Nº 1-2  2015  págs. 25 - 34
Autores: Sevillano, Juan Francisco; Arizti, Fernando José; et al.
ISSN 0026-2692  Vol. 44  Nº 10  2013  págs. 912 - 919
This paper presents a comparative study on time-to-digital converters (TDC) for their use as part of an RFID tag sensor. TDCs can digitize any physical magnitude previously converted to time delay and exploit the benefits of time domain conversion: high resolution with reduced power consumption and low voltage operation. Three different TDC architectures are analyzed and a calibration strategy tailored for RFID sensing applications is proposed in order to account for process variations. Converters implemented using a 0.18 mu m CMOS standard process have been analyzed at transistor level for human body temperature sensing applications. An accuracy of 0.011 degrees C is achieved in the range from 35 degrees C to 43 degrees C for the nonius TDC with a power consumption of only 4.1 nW at 10 samples per second from a 1.8 V voltage supply. (C) 2012 Elsevier Ltd. All rights reserved.
Autores: D'Souza, S.; Hsiao, F.; Tang, A.; et al.
ISSN 1549-7747  Vol. 60  Nº 8  2013  págs. 457 - 461
Autores: Beriain, Andoni; Solar, Héctor; et al.
ISSN 0026-2692  Vol. 43  Nº 10  2012  págs. 708 - 713
This paper presents a low power voltage limiter design for avoiding possible damages in the analog front-end of a RFID sensor due to voltage surges whenever readers and tags are close. The proposed voltage limiter design takes advantage of the implemented bandgap reference and voltage regulator blocks in order to provide low deviation of the limiting voltage due to temperature variation and process dispersion. The measured limiting voltage is 2.9 V with a voltage deviation of only +/- 0.065 V for the 12 measured dies. The measured current consumption is only 150 nA when the reader and the tag are far away, not limiting the sensitivity of the tag due to an undesired consumption in the voltage limiter. The circuit is implemented on a low cost 2P4M 0.35 mu m CMOS technology. (C) 2012 Elsevier Ltd. All rights reserved.
Autores: Liu, J.Y.C.; Berenguer, Roque José; Chang, M.C.F.;
ISSN 0018-9480  Vol. 60  Nº 5  2012  págs. 1342 - 1352
A self-healing two-stage millimeter-wave broadband power amplifier (PA) with on-chip amplitude/phase compensation is realized in 65-nm CMOS. The amplitude and phase compensations are accomplished by using feedback bias/capacitive schemes to extend the linear operation region and optimize the PA efficiency. Tunable control knobs are inserted in the linearization block to enhance the PA performance yield against process/temperature variations and device ageing effects. This prototype shows a 5.5-dB improvement of the output 1-dB compression point (P-1dB) and a less than 2% chip-to-chip gain variation. At a 1-V supply, the differential PA achieves a saturation output power (P-sat) of 14.85 dBm with a peak power-added-efficiency (PAE) of 16.2%. With the amplitude compensation, P-1dB is increased to 13.7 dBm. With the phase compensation, the output phase variation is decreased to less than 0.5 degrees. To the best of our knowledge, this prototype provides the highest P-sat and P-1dB with simultaneously high PAE from a single PA reported to date. The PA delivers a linear gain of 9.7 dB and has a 7-GHz 3-dB bandwidth from 55.5 to 62.5 GHz with a compact total area of 0.042 mm(2).
Autores: Gonzalez, J.; Solar, Héctor; Adin, Íñigo; et al.
ISSN 0018-9480  Vol. 59  Nº 9  2011  págs. 2318 - 2330
A decreasing-sized pi-model electrostatic discharge (ESD) protection structure is presented and applied to protect against ESD stresses at the RF input pad of an ultra-low power CMOS front-end operating in the 2.4-GHz industrial-scientific-medical band. The proposed ESD protection structure is composed of a pair of ESD devices located near the RF pad, another pair close to the core circuit, and a high-quality integrated inductor connecting these two pairs. This structure can sustain a human body-model ESD level higher than 16 kV and a machine-model ESD level higher than 1 kV without degrading the RF performance of the front-end. A combined on-wafer transmission line pulse and RF test methodology for RF circuits is also presented confirming previous results. The front-end implements a zero-IF receiver. It has been implemented in a standard 2P6M 0.18-mu m CMOS process. It exhibits a voltage gain of 24 dB and a single-sideband noise figure of 8.4 dB, which make it suitable for most of the 2.4-GHz wireless short-range communication transceivers. The power consumption is only 1.06 mW from a 1.2-V voltage supply.
Autores: Solar, Héctor; Bistue, G.; et al.
ISSN 1751-8725  Vol. 5  Nº 7  2011  págs. 795 - 803
A model for fully integrated CMOS linear power amplifiers (PAs) is presented. The model predicts the performance of the CMOS PA in terms of power-added efficiency (PAE) and output power (P-OUT) with respect to the main design parameters, such as supply voltage, current consumption, gain and inductor quality factors (Qs). In order to demonstrate the usefulness of the model, several studies showing the impact of these design parameters on the PA performance are presented. Finally, a 0.18 mu m fully integrated CMOS PA has been fabricated and compared with the model, showing good agreement. The fabricated PA presents 23 dBm of 1 dB compression point (P-1dB) and 27 dBm of saturated power (P-SAT) at 4.2 GHz with high maximum PAE of 32%.
Autores: Liu, G.; Berenguer, Roque José; Xu, Y.;
ISSN 1549-7747  Vol. 58  Nº 12  2011  págs. 842 - 846
This paper describes the modeling and the design of a ladder-structured multilayer-coplanar-waveguide-based tunable differential inductor with wide tuning range and high quality factor. The impacts of process variation on the performance of the inductor and active components are mitigated through postfabrication tuning. A configurable 77-GHz voltage-controlled oscillator (VCO) with a tunable inductor has been designed and implemented in a 65-nm single-poly six-metal bulk CMOS technology. Techniques for tuning the center frequency and increasing the tuning range are described. Under a 1.5-V supply, the measured VCO can be tuned from 67.3 to 77.9 GHz, i.e., 15.8%, while consuming 14.3 mW; the output power is -4.5 dBm, and the phase noise at a 10-MHz offset from the 77-GHz carrier is -108.4 dBc/Hz. This configurable VCO provides a wide tuning range and immunity to process variation.
Autores: Alvarado, Unai; Berenguer, Roque José; Adin, Íñigo; et al.
ISSN 0098-9886  Vol. 38  Nº 2  2010  págs. 123 - 129
Low-frequency (flicker) noise is one of the most important issues in the design of direct-conversion zero-IF front-ends. Within the front-end building blocks, the direct-conversion mixer is critical in terms of flicker noise, since it performs the signal down-conversion to baseband. This paper analyzes the main sources of low-frequency noise in Gilbert-cell-based direct-conversion mixers, and several issues for minimizing the flicker noise while keeping a good mixer performance in terms of gain, noise figure and power consumption are introduced in a quantitative manner. In order to verify these issues, a CMOS Gilbert-cell-based zero-IF mixer has been fabricated and measured. A flicker noise as low as 10.4 dB is achieved (NF at 10 kHz) with a power consumption of only 2 mA from a 2.7 V power supply. More than 14.6 dB conversion gain and noise figure lower than 9 dB (DSB) are obtained from DC to 2.5 GHz with an LO power of -10 dBm, which makes this mixer suitable for a multi-standard low-power zero-IF front-end. Copyright (C) 2008 John Wiley & Sons, Ltd.
Autores: Berenguer, Roque José; Liu, G.; Xu. I.;
ISSN 1531-1309  Vol. 20  Nº 12  2010  págs. 678 - 680
Autores: Zalbide, Ibon; et al.
ISSN 1549-7747  Vol. 57  Nº 2  2010  págs. 95 - 99
A long-range UHF RF identification (RFID) sensor has been designed using a 0.35-mu m CMOS standard process. The power-optimized tag, combined with the ultralow-power temperature sensor, allows an ID and a temperature reading range of 2 m from a 2-W effective radiated power output power reader. The temperature sensor is based on a ring oscillator, where the temperature dependence of the oscillation frequency is used for thermal sensing. The temperature sensor exhibits a resolution of 0.035 degrees C and an inaccuracy value lower than 0.1 degrees C in the range from 35 degrees C to 45 degrees C after two-point calibration. The average power consumption of the temperature sensor is only 110 nW at ten conversions per second while keeping a high resolution and accuracy. These properties allow the use of the RFID as a batteryless sensor in a wireless human body temperature monitoring system.
Autores: Berenguer, Roque José; Rebollo, I.; Zalbide, I.; et al.
Libro:  Wirelessly powred sensor networks and computational RFID
2013  págs. 79 - 112
Autores: del Río, David; Rezola, Ainhoa; Sevillano, Juan Francisco; et al.
This book presents design methods and considerations for digitally-assisted wideband millimeter-wave transmitters. It addresses comprehensively both RF design and digital implementation simultaneously, in order to design energy- and cost-efficient high-performance transmitters for mm-wave high-speed communications. It covers the complete design flow, from link budget assessment to the transistor-level design of different RF front-end blocks, such as mixers and power amplifiers, presenting different alternatives and discussing the existing trade-offs. The authors also analyze the effect of the imperfections of these blocks in the overall performance, while describing techniques to correct and compensate for them digitally. Well-known techniques are revisited, and some new ones are described, giving examples of their applications and proving them in real integrated circuits.
Autores: Solar, Héctor; Berenguer, Roque José;
The work establishes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focuses on design guidelines of the inductor¿s geometrical characteristics for power applications and covers their measurement and characterization. Additionally, a model is proposed which would facilitate designs in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers limitations that CMOS processes can impose on implementation. The book also provides different techniques and architectures that allow for optimization.