Nuestros investigadores

Unai Alvarado Videira

Publicaciones científicas más recientes (desde 2010)

Autores: Adin, Íñigo; Arrizabalaga, Saioa; et al.
ISSN 0263-2241  Vol. 77  2016  págs. 124 - 131
The interoperability between on track balises and the on board Balise Transmission Module systems depends on both sides' susceptibility and allowed emissions. For that assessment, the document that governs the testing methodology, tools and procedures (Subset 116) needs to be completed prior to its publication. The present paper proposes an advance beyond the state of the art for the rolling stock emission assessment in terms of the test setup and of the post-processing procedure. The documentation commonly used in ERTMS-related issues has been analyzed and the common tools and procedures have been taken into consideration for the proposal presented by the authors. (C) 2015 Elsevier Ltd. All rights reserved.
Autores: Alvarado, Unai; Juanicorena, Aitor; Adin, Íñigo; et al.
ISSN 2161-3915  Vol. 23  Nº 8  2012  págs. 728 - 741
Power consumption is one of the most critical issues when designing low-cost electronic devices, such as sensing nodes in wireless sensor networks. To support their operation, such systems usually contain a battery; however, when the battery has consumed all its energy, the node (e.g. the sensor) must be retrieved and the battery replaced. If the node is located in a remote and non-accessible placement, battery replacement can become an expensive (and even impossible) task. This way, energy harvesting has emerged as a suitable alternative to supply low-power electronic systems, by converting ambient energy into electric power. Scavenged energy can be used to directly supply the circuits, or stored to be used when needed. This paper summarises the power needs of a general wireless sensor node and describes the main principles of most representative energy harvesting technologies. Copyright (c) 2012 John Wiley & Sons, Ltd.
Autores: Alvarado, Unai; Berenguer, Roque José; Adin, Íñigo; et al.
ISSN 0098-9886  Vol. 38  Nº 2  2010  págs. 123 - 129
Low-frequency (flicker) noise is one of the most important issues in the design of direct-conversion zero-IF front-ends. Within the front-end building blocks, the direct-conversion mixer is critical in terms of flicker noise, since it performs the signal down-conversion to baseband. This paper analyzes the main sources of low-frequency noise in Gilbert-cell-based direct-conversion mixers, and several issues for minimizing the flicker noise while keeping a good mixer performance in terms of gain, noise figure and power consumption are introduced in a quantitative manner. In order to verify these issues, a CMOS Gilbert-cell-based zero-IF mixer has been fabricated and measured. A flicker noise as low as 10.4 dB is achieved (NF at 10 kHz) with a power consumption of only 2 mA from a 2.7 V power supply. More than 14.6 dB conversion gain and noise figure lower than 9 dB (DSB) are obtained from DC to 2.5 GHz with an LO power of -10 dBm, which makes this mixer suitable for a multi-standard low-power zero-IF front-end. Copyright (C) 2008 John Wiley & Sons, Ltd.
Autores: Khemchandani, S.L.; del Pino, J.; Lopez-Morillo, E.; et al.
ISSN 0925-1030  Vol. 65  Nº 1  2010  págs. 1 - 14
This paper presents a tutorial on RF and mixed signal circuits design for a digital video broadcasting-handheld tuner. A detailed description of the wideband low noise amplifier, the mixer, the synthesizer and the ADC, which are the most challenging components of a receiver, are carried out. Requirements relative to frequency range, sensitivity, noise figure, linearity, phase noise gain and dynamic range are discussed. The LNA uses a cascode configuration, combining a resistive loaded LNA with a conventional resistive Shunt-feedback, in order to achieve a low power, low noise and wide bandwidth. The mixer uses a classical Gilbert cell configuration. The VCO employs techniques like emitter degeneration, capacitor divider, and optimum bias for minimum noise to improve phase noise requirements and oscillation amplitude. There are two ADC structures, one of which is a delta sigma ADC. The blocks are implemented in a AMS 0.35 mu m BiCMOS process.
Autores: Alvarado, Unai; Bistue, G.; Adin, Íñigo;