This letter presents the design of a 140-160 GHz vector-modulator-type phase shifter, integrated in a 55-nm BiCMOS technology. The circuit is optimized to minimize the occupied area and maximize the linearity, facilitating its integration in D-band phased arrays. Test results show an average insertion loss of 4.5 dB, an OP 1 dB of -3.7 dBm, and rms gain/phase errors lower than 1.4 dB and 7.5 degrees. The circuit core occupies 0.05 mm(2), consuming less than 66 mW of dc power.

Changes in ambient temperature or chip temperature result in variations in the in-phase and quadrature (I/Q) gain and phase imbalance. As a consequence, the overall system performance can be seriously degraded, especially in wideband multi-Gb/s systems, where the I/Q imbalance is highly selective in frequency. Unless appropriately considered, temperature drifts can decrease the image rejection ratio (IRR) of the transmitter. This article presents a novel compensation method for temperature-dependent transmitter I/Q imbalance over the entire temperature range. It consists of a simple predistortion technique that, based on a few factory characterizations of gain and phase imbalance, is able to estimate and correct the I/Q imbalance at any temperature, without interrupting the normal functionality of the system. The proposed method is assessed in a 2-GHz, 64-QAM transceiver implemented with real hardware. The measurements show that the proposed approach is able to keep the IRR greater than 35 dB in the entire bandwidth and an error vector magnitude (EVM) lower than 3 over a temperature range of 70 C.

This work presents a nonius time to digital converter (TDC) adapted to a passive RF identification (RFID) pressure sensor tag. The proposed converter exploits the characteristics of time-based sensor interfaces and allows reducing voltage supply and power consumption while maintaining resolution and conversion efficiency. The nonius TDC has been designed and fabricated using the TSMC 90 nm standard CMOS technology. The main blocks of the converter are described and both the resolution adjustment and measurement processes are explained in detail. Measurement results show 10.49 bits of effective resolution for an input time range from 28.19 to 42.93 mu s. With a sampling rate of 19 KS/s the converter has a conversion efficiency of 0.395 pJ/bit with a voltage supply of only 0.6 V. This characteristics in the proposed nonius TDC enables an increased reading range of the passive RFID pressure sensor tag.

This letter presents a 15-21 GHz I/Q upconverter, based on two Gilbert-cell mixers with an on-chip wideband linearization loop that extends the linear region and allows power efficient operation at backoff power levels. A quadrature LO signal is generated using an integrated two-stage polyphase filter. Measurements show a conversion gain of -5.5 dB, an output 1-dB compression point of 0 dBm, and an image suppression of 40 dB over the 6-GHz output bandwidth. An error vector magnitude of 3.5% is obtained for a 10-Gb/s 64-QAM signal with a bandwidth of 2 GHz. The circuit is integrated in a 55-nm BiCMOS process and occupies 1.07 mm2. The dc power consumption is 61 mW.

This paper presents the design of a wideband and high-linearity E-band transmitter integrated in a 55-nm SiGe BiCMOS technology. It consists of a double-balanced bipolar ring mixer which upconverts a 16-21-GHz IF signal to the 71-76- and 81-86-GHz bands by the use of a 55/65-GHz local oscillator signal, followed by a broadband power amplifier which employs 2-way output power combining using an integrated low-loss balun transformer. The transmitter exhibits an average conversion gain of 24 dB and 22 dB at the 71-76- and 81-86-GHz bands, respectively, with an output 1-dB compression point greater than 14 and 11.5 dBm at each band. A maximum output power of 16.8 dBm is measured at 71 GHz. The dc power consumption is 575 mW. The presented transmitter is used to demonstrate the transmission of a 10.12-Gb/s 64 quadrature amplitude modulated signal with a spectral efficiency of 5.06 bit/s/Hz, which makes it suitable for use in future highcapacity backhaul and fronthaul point-to-point links.

This paper addresses the estimation and compensation of I/Q imbalance, one of the most prominent impairments found in wideband zero-intermediate frequency transceivers (TRxs). The I/Q imbalance encountered in this kind of TRx comprises not only frequency-selective gain and phase imbalance but also delay imbalance. Unless appropriate compensation is applied, the I/Q imbalance significantly degrades the performance of a communication system. This paper presents a novel compensation technique for transmitter I/Q imbalance based on built-in-self-calibration, a low cost and robust compensation technique that enables manufacturing as well as in-field calibration with low computational complexity. The method's performance is evaluated in a TRx with 64-quadratic-amplitude modulation and 2 GHz of bandwidth implemented with real hardware. The measurements show that the proposed technique achieves an image rejection ratio greater than 35 dB in the entire 2 GHz bandwidth and an error vector magnitude lower than 3%.

Millimeter wave links are an attractive solution for mobile network backhaul. In order to cope with the requirements of future networks, these millimeter wave links should achieve Gigabit data rates. These data rates can be achieved by using wide-band and high order modulations in E-Band. Heterodyne architectures are good candidates for integrated transceivers, but, the design of integrated transceivers at these frequencies is a challenging issue. An important source of degradation is I/Q imbalance, which can significantly reduce the performance of a communication system with zero-second-IF transceivers if it is not appropriately compensated. The article analyzes the source of this IQ imbalance and proposes the use of different digital processing techniques, including a linear adaptive equalizer scheme. The performance of the transceiver is analyzed at system level by means of simulations. The results presented in the article suggest that the use of those techniques is able to mitigate the impact of the IQ imbalance effects, in order to allow the use of a high-order modulation such as 64QAM.

This paper presents an area-efficient variable-length FFT algorithm for DVB-T2 receivers. A matrix-based approach is used to achieve a novel radix 2(8) algorithm that fulfils the DVB-T2 specifications. Several implementation techniques are proposed to apply in order to reduce the FFT core area, such as a variable datapath scaling approach, a memoryless CORDIC algorithm and an efficient FIFO implementation. The layout of the FFT processor is designed in XFAB 0.18 mu m CMOS technology. The proposed variable-length processor occupies a layout area of 6.75 mm(2). Compared with the DVB-T2 designs in the literature, the proposed FFT processor presents the most area-efficient implementation. Furthermore, it provides a good power efficiency in the lower modes.

This paper presents a comparative study on time-to-digital converters (TDC) for their use as part of an RFID tag sensor. TDCs can digitize any physical magnitude previously converted to time delay and exploit the benefits of time domain conversion: high resolution with reduced power consumption and low voltage operation. Three different TDC architectures are analyzed and a calibration strategy tailored for RFID sensing applications is proposed in order to account for process variations. Converters implemented using a 0.18 mu m CMOS standard process have been analyzed at transistor level for human body temperature sensing applications. An accuracy of 0.011 degrees C is achieved in the range from 35 degrees C to 43 degrees C for the nonius TDC with a power consumption of only 4.1 nW at 10 samples per second from a 1.8 V voltage supply. (C) 2012 Elsevier Ltd. All rights reserved.

This book presents design methods and considerations for digitally-assisted wideband millimeter-wave transmitters. It addresses comprehensively both RF design and digital implementation simultaneously, in order to design energy- and cost-efficient high-performance transmitters for mm-wave high-speed communications. It covers the complete design flow, from link budget assessment to the transistor-level design of different RF front-end blocks, such as mixers and power amplifiers, presenting different alternatives and discussing the existing trade-offs. The authors also analyze the effect of the imperfections of these blocks in the overall performance, while describing techniques to correct and compensate for them digitally. Well-known techniques are revisited, and some new ones are described, giving examples of their applications and proving them in real integrated circuits.